When you walk into a data center and see thousands of cables connecting endless rows of servers, you’re only viewing the tip of the bandwidth iceberg. The real bandwidth revolution is happening inside the semiconductor chip packages driving those connections. 

Wolfgang Sauter, Senior Distinguished Engineer at Marvell Technology, takes us deeper into the world of advanced semiconductor packaging, where the future of AI and data processing is being built on ever higher density chip connections. From 3D chip stacking that packs more performance and memory bandwidth into the same footprint to co-packaged optics that bring higher bandwidth directly onto the processor, Sauter reveals how chip packaging has evolved from a simple protective housing to the key driver of next-generation computing. 

In this episode of Manufacturing Matters, Sauter sits down with TECH B2B Marketing’s Aaron Hand and Dan McCarthy to explore the manufacturing challenges of connecting chips and chiplets, cooling 4-kilowatt modules, and why the packaging for today’s processors has become as critical than the silicon inside them. 

Dan McCarthy: [00:00:02] Hello, everyone. Welcome back to “Manufacturing Matters” podcast, where we talk about the trends and technologies shaping global industry and logistics and other sectors of the economy. I’m Dan McCarthy of Tech B2B Marketing. Joining me today are my colleague, Aaron Hand. Say hi Aaron.

 

Aaron Hand: [00:00:19] Howdy.

 

Dan McCarthy: [00:00:20] Wolfgang Sauter, senior distinguished engineer at Marvell Technology. We’re delighted to have him here today because Marvell is a big player in the area of semiconductors as well as data centers. We have a lot to talk  about today, a lot of ground to cover. So,  welcome to the podcast, Wolfgang. Thanks for joining us.

 

Wolfgang Sauter: [00:00:39] Great. Thanks for the welcome.

 

Dan McCarthy: [00:00:42] Before we kick off, and get into the deep dive of the technology, let’s just start off by telling us a little bit about Marvell Technology–what it does, where it fits into the semiconductor space, and what you do.

 

Wolfgang Sauter: [00:00:56] Okay. Okay, good. Yeah. So, I’m a packaging guy. Let’s start there, and let me first go to the company and then come back to what do I do. So, Marvell is a fabless semiconductor company. We focus on what we call data infrastructure products. We don’t make consumer products, so for some of your listening audience, Marvell may be potentially be a less known name just because you don’t see it on the street. You don’t carry devices around that carry our brand. But our chips go into the data centers, into all the places where the data that comes from your devices routes through, gets stored, gets processed, etc. So, kind of in the buildings that you don’t see. So, that’s why it’s not such a street name, but it’s a pretty well-known name and a big player in the custom chip design for AI, for data center, and other infrastructure aspects. Now, I did just mention custom. So, coming back around to, what do I do? What does my team do? We are a fairly small team of technologists, and we cover the entire spectrum of a chip life cycle. So, if you think about a chip from beginning to end, there’s architecture, there’s IP, there’s packaging, there’s quality, there’s yield, there’s manufacturing. A lot of different aspects. Our team covers all of these aspects with experts from all disciplines. And we are kind of the first front of the company when we talk to our data center customers. So, we work directly with these customers on what is it they need for the next generation? Which direction is the industry going? And then also bringing that back into the company, aligning Marvell’s roadmap for the technology. What do we need for IP development? What do we need for technology development and driving that, so that our roadmap for the next two to five years lines up with what our customers need and having a superior solution for our customers.

 

Dan McCarthy: [00:03:04] Great. Well, we’re talking to the right guy on trends and technology. I know what you do expands beyond the data center, but I wanted to actually focus a little bit on that first because I know there’s some developments there in packaging that I think are particularly interesting. But before we do, a little bit of context for our listeners, you got a lot of trends demanding more bandwidth in the data center. You have AI, crypto, all these things are pushing for more bandwidth in the data center. And a lot of that comes down to streamlining the electrical and optical conversions within the pluggable transceivers that connect the thousands of servers and switches in those data centers. Streamlining that comes down to how those electrical and optical functions are packaged, right? So, that’s wjy we’re talking to you today. Maybe you could take it from there and explain or provide us some context on why next generation chip packaging is so critical to pushing, or enabling, the push to 1.6 terabyte transceivers.

 

Wolfgang Sauter: [00:04:02] Okay. Okay, good. And if I may, maybe I can rewind us a little bit and step back a little bit. You mentioned very specifically the 1.6T transceiver. And I first want to kind of separate the different areas of interconnect and where the bandwidth that you just mentioned may be needed. So, there’s bandwidth in the data center that you kind of see, right? You look in the data center, there is all these black cabinets full of cables, thousands of cables coming out. So, that is where we talk about the transceivers. They connect rack to rack and tray to tray in a data center. That’s very visible. That’s kind of what you, what you maybe think about as as the interconnect. But then there is also a very different type of a bandwidth discussion and that is inside the package. If you go inside a tray, you go inside the XPU, and inside the XPU there is generally there’s pretty much never today just one chip in there. There’s always several chips, including memories, in there. And there’s tremendous bandwidth requiremen–how much data you have to push around from one chip to the next chip within the package. I’m sure we’ll come back to, to the whole chiplet discussion later in this, in this podcast. But I wanted to first differentiate a little bit. There is these two very, very separate areas. The one that you see when you walk in a data center. And then there is the other one that you don’t really see because it’s inside a tray, inside a package.

 

Wolfgang Sauter: [00:05:33] And that is really generally referred to as advanced packaging. So, most of what we do is happening inside that. Now, if we want to go a little bit into the 1.6T, that is obviously a very, very challenging part. It’s a subdiscipline, I want to say of, of advanced packaging. And it’s really challenging in many, many different ways. It is a very small form factor. It has thermal challenges. The data rate goes up every generation. It pretty much doubles every generation. It was 400, now it’s 800, now it’s 1.6T in development. All of these drive advanced packaging by itself, but it’s again, a very customized, small element, with the challenges really being very small form factor, very precise alignment of fibers, thermal management, and then how do you contain  all of these challenges in this very, very small small form factor. Now, if we think about going forward, how  does that intersect maybe, you know, the bigger scope of advanced packaging and the XPU? There’s a lot of discussion about co-packaged optics. And that will then move the transceiver from where you see it today, right? The backplane or the front plane, where you see the cables coming out, move it from there to inside the tray and right onto the package where the XPU sits. And that’s then called co-packaged optics, when you move the optics onto the package. And that has additional power benefits if it’s used in the right way.

 

Dan McCarthy: [00:07:30] Okay. Right. And so just a I’m sorry. Go ahead, Aaron.

 

Aaron Hand: [00:07:34] No, no. Go ahead. I just, I wanted to kind of jump in with with some packaging questions, kind of get a look at where packaging lies in general, but  Dan, did you have a specific follow-up question there with, with CPOS?

 

Dan McCarthy: [00:07:51] No, I was just going to add a nuance to co-packaged optics, but it can wait. We’ll come back to it.

 

Aaron Hand: [00:07:59] Okay. [00:07:59] This might be a good area for making cuts, Mike. [00:08:02] So, Wolfgang. One other thing I wanted to kind of pull back a little further, too, and  take a look at some of the packaging options that are out there and, and how these, you know, you mentioned about how most chips have multiple chips inside them. I have been hearing a lot about chiplets in general, which is the general idea being that you’re not printing all of those semiconductor lines just on one die. You’ve got multiple die within  that package. So, maybe you could kind of talk a bit about that idea of chiplets and explain the advantages of having multiple die within that package?

 

Wolfgang Sauter: [00:08:50] Okay. Yeah, sure. And want to again make sure. Let’s talk about the XPU first because that’s really where most of it is happening. If you were to be able to see inside a data center, inside a tray, and open up the module, you would see that there is today several chips in there, including memories. Right? It’s even today, and one or more of these chips will actually be the compute die. And that is kind of the interesting part, is an architect of, of an XPU will always fill up the radical, right. That’s just what architects do. If you can make something on one chip, you will.

 

Dan McCarthy: [00:09:41] Okay.

 

Wolfgang Sauter: [00:09:42] The problem is, if you can’t, right? And that’s that’s the world we’re in today. You can’t fit all the content anymore into one single radical, which means you need more than one chip. So chiplets are, I would say, in that perspective, less driven out of opportunity but out of necessity. You just can’t build it any other way. If you were to sum up all the content that’s in one of these XPUs, including all the memory and DRAM die, you have an area that’s probably about this big. It’s gigantic. So, there is one part of chiplets that is, as I described, you know, architects will always fill up the chiplet, or the the main die, the compute die. So, from a yield or cost perspective, that doesn’t really improve anything. Right? Because you are filling up the radical. You’re going to drive that to 2 nanometer or beyond in the most advanced node. So, the yield is going to be absolutely awful on that thing, always. And that’s because the architects want to stay on a monolithic die. Now, the other part of it is all the other functions. So, let’s say everything else that is not compute, that is the content you will shift onto surrounding chiplets.

 

Wolfgang Sauter: [00:11:02] So, for example, I/O. And the parts–those will benefit from being smaller. So, there is a yield in cost benefit in that aspect. There is also the additional benefit that you’ve now become flexible. You don’t have to build that chiplet in the same technology node anymore. You can build that in a previous technology node. So, again cost reduction opportunity. You combine a 2 nanometer compute die with a 3 or 5 nanometer I/O die. And the other advantage, and that’s probably the biggest advantage, is the time to market advantage because as you develop technology, one of the longest poles is IP development. How do you communicate all the I/O long reach service? Very high-speed service takes a long time to develop and to qualify. And if you can use an existing chiplet in an older node that you’ve already qualified, that doesn’t scale well anyway to newer nodes, you have a huge advantage in time to market. So, that’s really the chiplet advantage. Less opportunistic as it’s often described in the industry, but a necessity. And you use it where it really provides value.

 

Dan McCarthy: [00:12:16] Does that introduce more manufacturing challenges versus today’s packaging?

 

Wolfgang Sauter: [00:12:23] Well, I would say today we’re there already. But if you compare it to yesterday’s packaging, yesterday’s packaging, you had one chip and one package. Very, very simple. Very simple. Today you have several chips in one package that generally need to be integrated on an interposer 2.5D solution. Significantly more complex and very, very expensive.

 

Dan McCarthy: [00:12:48] Okay. You mentioned interposers. Marvell recently launched a new interposer platform that packs a lot of functionality into that semiconductor package. I’m going to let you summarize the details, but my question is whether the primary driver for that was based on improving pluggable or overall chip performance, or was it just smoothing the manufacturing challenges on chiplet packaging, or both? What was the driver there?

 

Wolfgang Sauter: [00:13:14] It’s really an ecosystem question. So, if you look at today’s manufacturing environment, you have a clear leader [00:13:28] out there in TSMC. [00:13:29] Phenomenal technology, far out ahead, but it’s not cheap. And then all the OSATs that have historically been the companies who package the products are kind of on the sideline watching. And, and so we’ve partnered with multiple of them to bring them up to a level where we can use them on the XPU products and establish an ecosystem that is sufficient to address some of the market, at least. I think the industry leaders will remain leaders because as you bring up kind of the second-, third-source suppliers, the leaders will always march ahead and create the next offering and continue to be in the lead. So, there’ll always be a first adopter and then a follow-up ecosystem.

 

Dan McCarthy: [00:14:27] Tell us a little bit more about the technologies that the interposer–is that what that is? Is that what you’re defining as the ecosystem . . .

 

Wolfgang Sauter: [00:14:34] Yeah. Yeah. Exactly. Yeah. So to, to connect these chips together. . . And that’s where we come back around to what I said in the beginning. The advanced packaging is really happening inside the XPU. So, you have multiple, you know, radical-sized die with some I/O die and high-bandwidth memories. And the interconnect between them requires such high bandwidth that you need thousands of wires, sometimes tens of thousands of wires, to connect these together. And the only way to connect them together is with very, very fine lines and spaces. So, typical package could never do that. So you need something that’s built in a fab-like environment or built, you know, 2-micron line space over seven or eight layers to connect them all together.

 

Dan McCarthy: [00:15:22] Okay. And does this also accommodate the optical connections. Would this squalify as co-packaged optics or is it separate?

 

Wolfgang Sauter: [00:15:32] Yeah. Yeah. It’s a little bit separate. Generally, the optical components may go straight to a 3D-type integration rather than 2.5D integration. There isn’t a “one thing solves all” problems. The 2.5D integration is really for a large area integration. If you have a lot of components that you need this large span, a large area, versus 3D is more of a very space-constrained environment, and you just can’t grow out of that. You need to grow in the vertical rather than horizontal.

 

Aaron Hand: [00:16:12] Yeah, and I did want to get into that a bit too, about kind of the differences between 3D packaging, for example, and, and 2.5D. So, 3D is really stacking on top of each other. And then you have to have those interconnects with through silicon vias or bumps to make those connections, correct? Whereas 2.5D spreads more horizontally?

 

Wolfgang Sauter: [00:16:35] Yeah, that is correct. Yeah, yeah.

 

Aaron Hand: [00:16:38] Okay. So,I mean, 3D is really out of necessity, right? If you don’t have the space to spread horizontally, are there other advantages for, for going to a 3D package?

 

Wolfgang Sauter: [00:16:51] There is. Yeah. Yeah. Because the interconnect pitch in a 3D orientation is much, much denser than in a 2.5D, and it’s also much, much shorter. So, essentially a 3D die acts almost like a single die. Right? So you can take, where I started earlier. Architects always want to stay within one chip if they can. So, now you essentially build two chips in the size of one because you have this incredible interconnectivity between those two chips. It is, however, very, very complex to do 3D. We’ve already taped out our first multicore processor in a 3D fashion, recently, and we learned a lot through it. It’s very, very difficult. And you have to prepare for it for a long, long time because you really have to think about it. A 3D today, true 3D, meaning it’s hybrid bonded and it’s in a face-to-face configuration, meaning an active side of a die faces another active side of a die. And then the bottom die that is now face up. So, it’s flipped up from what it was previously, but usually active side was down. Now active side is up. You have to think about, as you develop the IP, how do you escape signals from the bottom die because they can’t just come out anymore as they did before. They actually have to go through the silicon before they can escape. So, all of your IP, as you develop the IP, needs to consider that and that space for the TSVs and that escape has to be built in as you develop the IP, which as I mentioned before, is always the long pole in the tent, right? So, you know, years before you actually want to use it on a product, you have to lay out your IP already considering that.

 

Aaron Hand: [00:18:50] Yeah. Which frankly, all of this stuff just absolutely fascinates me. The amount of complexity that you’re dealing with and, and the solutions that engineers have come up with and designers have come up with just to solve all these issues. Just the sheer complexity, I think is, is a big enough issue. But then are you also dealing with other ramifications of that? Are there heat dissipation problems, for example?

 

Wolfgang Sauter: [00:19:19] Great question. Absolutely. Thermal has always been considered the biggest challenge for 3D design, and thermal is challenging today, even in a 2.5D configuration, it’s really, really challenging to cool these chips. Next generation chips we expect to be, or modules, to be in the 4 kilowatt range. It’s absolutely incredible. And then you have several of those in one tray. So, cooling that is an absolute masterpiece, really. And now you want to double that essentially by stacking them on top of each other in the same geometry. You have twice as much power if you were to stack compute on top of compute. That just can’t be cooled anymore. So, you have to be very careful as you consider 3D. How do you architect so that you don’t stack something high power on top of something else that’s high power. It just won’t work. And it won’t work for two reasons. One is thermal, so power out, but the other one is power in. How do you get enough power in without burning up your your interconnects?

 

Aaron Hand: [00:20:28] Wow.

 

Dan McCarthy: [00:20:29] That chip that you’re taping out now or what is the application, the target application for that. Is that data center or is it anotherr sector?

 

Wolfgang Sauter: [00:20:39] It’s a processor. Yeah, it’s  not a full-blown product that will go into production, but it’s our first prototype of a process in 3D, and it’s very carefully architected. So, that one layer has compute, and the other layer has lower power in that area.

 

Dan McCarthy: [00:20:58] Okay.

 

Aaron Hand: [00:20:59] So, you talked about lessons learned. Can you give examples of somewhere maybe a direction you’ve gone and you say, nope, that’s not going to work? We’re not going to back up and come at this from a different angle.

 

Wolfgang Sauter: [00:21:12] I think there were certainly many lessons learned along the way. I think none of them have been completely revolutionary. So, I don’t think there’s any fundamental shift in how we approach things. I think we plan fairly well for it. And and it’s in the fab. So, maybe ask me again in six months.

 

Aaron Hand: [00:21:35] Great. So, then I guess, to get into the, the 2.5D Aspects. This is where your interposer platform fits in. Is  that right?

 

Wolfgang Sauter: [00:21:48] That is correct. Yeah, yeah.

 

Aaron Hand: [00:21:49] Okay. So, where do you see the trade-offs there? You know, how is that 2.5D technology working for you? And what are the challenges and advantages there?

 

Wolfgang Sauter: [00:22:03] Yeah. Yeah. So, 2.5D, if we just rewind 10 years ago, it didn’t exist essentially. It was when we had, we were IBM at the time, and we had a product in 2.5D, but it was incredibly complicated, was incredibly expensive. It wasn’t mainstream. And now if you go to today, it is a mainstream technology. Every single GPU out there is 2.5D. Every product that has an HBM memory is 2.5D. It really has become mainstream technology. There is what I mentioned before, that challenge of early adopter and the early technology availability. As we build these systems bigger and bigger and bigger, it’s very, very challenging to develop 2.5D solutions that can be so large and still assemble them onto an organic substrate. [00:23:02] And only TSMC really has the solution [00:23:05] right now to scale that to a bigger size. I think Intel is an alternative technology that can address that space. But all the other OSATs follow later. And that’s kind of the big challenge, is how can we accelerate getting them up proactively to the sizes we’ll need, not just the generation we’re building now but the generation afterwards and after that.

 

Dan McCarthy: [00:23:33] Are there other package types that should be on our radar? Fan-out wafer-level packaging, for example, or hybrid bonding? You talked about a little bit about, silicon bridges. I know there’s, it goes on and on. But I mean, in terms of what Marvell is working on. Do you see any demand drivers? These are unique solutions.

 

Wolfgang Sauter: [00:23:52] Yeah, we always have to be looking out for all of these technologies. I would say you mentioned silicon bridges, for example. So that is also a 2.5D technology that uses silicon bridges. There’s other technologies from the OSATs that use silicon bridges. [00:24:10] TSMC as a technology based on Silicon Bridge. [00:24:13] But there are 2.5D solutions of some type of shape. Same. Same with wafer-level fan-out. It’s just not processed on silicon. It’s processed on an organic basis. So, they’re all pretty, pretty similar. But I would say maybe is we’re monitoring all of those and we have to But really, I think the packaging technologies we have to look out for are the ones we don’t know yet. Right? What is the next game changer?

 

Dan McCarthy: [00:24:47] We’re just gonna jump back into co-packaged optics. Is that, I mean, I know that it’s gotten a lot of hype. And there’s that term, politely, but is it, do you see that as a future area where you you really need to invest? Is it something you sort of need to keep your eye on?

 

Wolfgang Sauter: [00:25:07] Co-packaged optics?

 

Dan McCarthy: [00:25:08] Yeah.

 

Wolfgang Sauter: [00:25:09] Absolutely. 100%. Yeah. Yeah, yeah. No we have  co-packaged optics technology, and it will come . . . In kind of rewinding back to where we started this discussion, there’s electrical interconnect and there’s optical interconnect. And there will always be a need for both. And the crossover point will shift over time. And that’s just a function of signal speed.

 

Wolfgang Sauter: [00:25:38] And so, today we can reach, you know, within a tray for sure, but then also tray to tray or within a rack, probably, for the most part electrically. But as we go to 200 gig instead of 100 gig and then to 400 gig instead of 200 gig–every time you double the speed of interconnect, you will only get half the distance if you go electrical. So, that crossover point towards CPO will shift over time. YYou will never be 100% in optical because if you go very short distance, you burn extra power. If you don’t need a repeater, you burn extra power, and you add extra cost and reliability concerns. So, you will never be all optical, but at the same time, you will also never be all electrical because you can’t get to the distance. They’ll coexist.

 

Dan McCarthy: [00:26:31] Where is it today in terms of the architecture of the tray in co-packaged optics? I mean, is it penetrating deeper toward the, you know, core silicon in the chips, or is it largely still around the perimeter?

 

Wolfgang Sauter: [00:26:47] Yeah, it’s still in the perimeter. It won’t make it onto a 2 nanometer compute die. Right. It’ll escape the compute complex and then you can drive either directly from an I/O chiplet into a co-packaged optics solution or have some type of re-driver in the CPO component itself.

 

Dan McCarthy: [00:27:13] You talked a little bit about you’re going to need optics, but it’ll never be entirely optical solution. So, the question, I think, for a lot of people is how quickly this is going to advance. How quickly it’s capable of advancing in terms of the manufacturing scalability, which prompted some thinking around. . . I know some analysts are talking about seeing a renaissance in copper-based solutions like direct copper attachments, electrical cables. Do you see that as slowing the progression of co-packaged optics down or replacing, complementing?

 

Wolfgang Sauter: [00:27:49] I think it’s really complementing. We actually do a ton of work on CPC. So co-packaged copper moving copper connectors onto the package. I don’t think that will necessarily delay or compete with the CPU because again, there will be both electrical and optical, and it just depends on the reach. How far, how far you need to go. So, they’ll coexist and the crossover point will continue to shift as we go up in speed.

 

Aaron Hand: [00:28:22] It’s just very interesting to me just to see, you know, which solution do we use. And the answer is yes. Right.

 

Wolfgang Sauter: [00:28:32] Yes.

 

Aaron Hand: [00:28:34] Everything has to come together and work together. All of these trade-offs and consequences. And you know, I think about the days I used to cover semiconductor manufacturing regularly for a good 12 years, but in those days it was, the package was just the plastic box around the die. It was just a protective and interconnect issue. And, and things have changed a ton since then so that package is just so instrumental in getting the performance you need. So, I’m kind of, I feel the need, at least for my brain, to back up here. And let’s look at those data centers and think about what your goals are there and how that package is affecting those goals. So, sorry, I’m coming at this kind of in a roundabout way, but I’m looking at, you know, compute density, thermal issues, and data centers being so energy intensive, power hungry. Does packaging affect all of those? Or where do you contribute, I guess?

 

Wolfgang Sauter: [00:29:43] Yeah, they affect absolutely all of them. Actually, if we kind of think about all the words we used in this conversation, right. We talked about 3D. We talked about die-to-die interfaces, partitioning, CPC, CPO, hybrid bonding. All of these are in the bucket packaging, right? And I mean, some of them are actually fab based. So you can kind of argue are they, are they fab, are they chip, are they packaged? It all becomes just one. But I think in our traditional use of, of the words and the languages, you would probably say that all of these changes are packaging, or at least integration driven. So, I think we’ve reached a point where packaging/integration really drives chip design and to a certain degree also system design today and becomes really the heart of of the whole system.

 

Aaron Hand: [00:30:37] So, are you able through packaging to help with the energy issue in data centers?

 

Wolfgang Sauter: [00:30:46] So, if we take the die-to-die interconnect. I mentioned we need an incredible amount of bandwidth between the compute die or the compute the I/0 die or compute to the memory, and that is a very significant portion of the energy burned. And optimizing that die to die is absolutely critical for these applications. So, that’s where we have probably the industry best die-to-die interface right now. And continuing to build on that because it is one of the biggest levers we have.

 

Aaron Hand: [00:31:23] Okay.

 

Dan McCarthy: [00:31:25] I know that packaging has become much more of an expense in the overall production. Is that because of the manufacturing of chips? Of chip packaging today? Is that where most of those costs come from, or is it more in the testing, other phases of production?

 

Wolfgang Sauter: [00:31:44] It’s really in the production. And I’m not sure that it’s all cost driven or to a large degree also price driven. As you say, historically, maybe packaging could have accounted for maybe 20% of the product cost. We’ve seen now cases where it’s like 40 to 50% of the product cost. It’s absolutely fascinating, what happened there. I think you’re hinting towards kind of also the ecosystem in the industry and how do you work with them.  And that has completely changed. If you, again, go back in time, probably only five years, the relationship between a customer with an [00:32:31] OSAT [00:32:32] was to beat them up every quarter, the QBR, and and squeeze every last penny out of them. And that relationship has completely changed. Today for the most part, I mentioned we have these very highly customized solutions and oftentimes not more than one supplier who can develop that particular solution. You need to come in with a very, very different approach. You have to treat them as a partner relationship. You either both win or you both lose. But it requires a very different skill set, a very different approach, a very different business environment, you know, compared to five years ago.

 

Dan McCarthy: [00:33:14] Yeah. On that note, I mean, it’s a very collaborative industry, much more than a lot of industries. It’s a lot of inputs globally. So, I guess I’m asking a very broad question. Are there emerging bottlenecks from the supply chain that are shaping the direction or are likely to shape the direction of advanced packaging?

 

Wolfgang Sauter: [00:33:36] I don’t think any new ones compared to what we’ve had in the last two or three years. But we are already pretty tight, right? Because there isn’t the copy exactly we had on previous technologies. We are in these very, very highly customized solutions that you get from one supplier. If they go through these incredible ramps up and it’s only a two-year, three-year production cycle, so there isn’t really time to develop many alternative technologies and solutions. There’s a very high level of codependence on being successful. So, that is the biggest challenge for the . . .

 

Dan McCarthy: [00:34:17] Okay. The codependence.

 

Wolfgang Sauter: [00:34:18] Yeah.

 

Dan McCarthy: [00:34:19] Okay. Is that landscape likely to change? If you know, the uncertainty around supply chains lasts longer, or is it sort of, I mean, is it a generational thing where the next generation reinvents? We’re reinventing it now, right? I mean, you’re developing all those technologies now. So, I guess, I guess, with the uncertainty, how do you plan ahead for the next phase of advanced packaging when the supply chain is so uncertain?

 

Wolfgang Sauter: [00:34:47] Yeah, yeah. I mean, there’s, and I’ll be just very, very direct. Right.  [00:34:52]TSMC is in the lead. And they will always [00:34:55] . . . if you have a product that has to ramp incredibly fast and only has a two- or three-year life cycle with extremely high volumes. It’s very hard to get around that as the default option. Intel is developing some very interesting technologies as well, or has developed and now optimizing that technology that could become very, very interesting. And then kind of all the other OSATs are always this half-step behind that makes it really hard for them to catch, you know, the ramp initially, but they could come in at the tail end of the production cycle. That’s how it works today.

 

Dan McCarthy: [00:35:42] So, this is very dense, very complicated topic. So, let me ask you a broad question. Is there anything we could expect further down the road for advanced packaging? What’s next? Is there anything we haven’t covered, I suppose, that we probably should have? What are you excited about?

 

Wolfgang Sauter: [00:35:57] Oh, there’s a ton, ton of different things, and it goes in all directions. So, we mentioned co-packaged copper a little bit. Right. So that itself drives a lot of complexity. You know, now all of a sudden you have cables coming out of a package. Now, how do you route them in a tray and in a rack? And how do you connect them? How do you test them? How do you do reliability, etc.? I think a different topic is integrated voltage regulator. Today the voltage regulators sit on the board, but that has some challenges of delivering power to the package. It would actually be much better if the voltage regulators were directly on the package, and that will happen. Also, we’re doing a lot of work in that space. Made a recent announcement also with several partners. And you know, once you do all that, once you get your electrical signals of the package and cables, you get your power conversion directly on the package. And then you look at your board and what’s left. There’s like almost nothing left on the board. I think that’s probably the most exciting view of, you know, how does the package take over more and more. Like we said, it takes over a lot more and more of the fab processing. And now how do we go the other direction, and how do we take over more and more of the whole system and system board aspect? That’s the really exciting part about packaging, that it grows in both directions very, very fast.

 

Dan McCarthy: [00:37:32] Sure.

 

Aaron Hand: [00:37:33] Wow.

 

Dan McCarthy: [00:37:35] Well, we could go on and on on this topic. I wish we could. I don’t want to take more of your time, but this has been a fascinating conversation. Is there anything else that we haven’t covered that before we go. We covered CPO active electronic cables. I think if we opened up the can of worms, we could be here all day. So, it’s been a fascinating conversation with you. I’m gonna give a big thank-you to you and Marvell for joining us today. Listeners, if you have any questions for Wolfgang, please feel free to post them in the LinkedIn thread for this podcast. If you’re interested in past episodes of “Manufacturing Matters,” you can find them on our website, manufacturing-matters.com, or your favorite podcast platform. And for anyone wishing to be in the loop on upcoming conversations about automation, please follow us on LinkedIn. And one more thank-you to Wolfgang for joining us today. Really appreciate your time, and thank you all for joining us.

 

Wolfgang Sauter: [00:38:32] Thank you. Great conversation.

 

Aaron Hand: [00:38:34] Thanks.

 

Dan McCarthy: [00:38:39]